Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBS) surrounded by a ring of programmable input/output blocks (IOBs). Some FPGAs also include additional logic blocks with special purposes (e.g., DLLs, RAM, and so forth).
FPGA logic blocks typically include programmable logic elements such as lookup tables (LUTs), memory elements, multiplexers, and so forth. The LUTs are typically implemented as RAM arrays in which values are stored during configuration (i.e., programming) of the FPGA. The flip-flops, multiplexers, and other components are also programmed by writing configuration data to configuration memory cells included in the logic block. For example, the configuration data bits can enable or disable elements, alter the aspect ratios of memory arrays, select latch or flip-flop functionality for a memory element, and so forth. The configuration data bits can also interconnect the logic elements in various ways within a logic block by programming select values for multiplexers inserted in the interconnect paths within the logic block.
The various logic blocks are interconnected by a programmable interconnect structure that includes a large number of programmable interconnect lines (e.g., metal wires). The interconnect lines and logic blocks are interconnected using programmable interconnect points (PIPs). For example, a PIP can be implemented as a CMOS pass-gate. When the passgate is turned on (i.e., the PIP is enabled), the two interconnect lines on either side of the passgate are electrically connected. When the passgate is turned off (i.e., the PIP is disabled), the two interconnect lines are isolated from each other. Thus, by controlling the values on the gate terminals of the PIPs, circuit connections can be easily made and altered. The value controlling each PIP is also stored in a configuration memory cell.
In FPGAs, configuration memory cells are typically implemented as static RAM (random access memory) cells. Each FPGA typically contains many thousands or even millions of these static RAM configuration memory cells.
When bombarded by high-energy particles, a static RAM cell can change state. For example, a stored high value can be inadvertently changed to a low value, and vice versa. These inadvertent and undesired state changes are known as “single event upsets”, or SEUs. Sometimes an SEU has no effect on the functionality of the design. At other times, an SEU can change the function of an FPGA such that the circuit implemented in the FPGA no longer functions properly.
For example, if a static RAM cell controlling a PIP changes state, but the two interconnect lines on either side of the PIP are not used in the design, this change of state has no effect on the function of the circuit. Similarly, a change of state in a memory cell in an unused LUT has no effect. However, when SEUs occur in portions of the FPGA that are in use, they can result in loss of function for the entire system that includes the FPGA.
In some applications, such as space-based applications in a low-earth orbit, it is important to minimize the effects of SEUs in FPGA-based designs. SEUs can also be a concern in some earth-based systems, e.g., systems in high altitude locations. One method of mitigating and minimizing these effects is “triple modular redundancy”, or TMR, in which three copies of a circuit are included in a design. Any two copies of the circuit can override output from the third copy, if it generates data different from the other copies. While useful in many applications, implementing a circuit using TMR requires about three times as many FPGA resources as a standard implementation. Therefore, when TMR is impractical, it is desirable to provide methods of measuring or estimating the susceptibility to SEUs of a design implemented in an FPGA. Using SEU susceptibility estimates, FPGA designers can judiciously trade off FPGA resources for reliability when implementing mitigation strategies.
In the absence of an accurate method of estimating the susceptibility of an FPGA design to SEUs, designers often resort to the worst case scenario and assume that an SEU at any configuration memory cell will interfere with the functionality of the design. However, this approach results in a susceptibility estimate that is much too high. As described above, some SEUs have no effect on the functionality of the design. Therefore, methods have been sought to produce more accurate estimates of SEU susceptibility, tailored to specific designs. Thus, one method of estimating the effects of SEUs is to test each FPGA design for susceptibility to SEUs. Further, based on the results of these tests, design strategies can be developed that inherently reduce the susceptibility of designs to SEUs.
Currently-known methods of performing such tests use an SEU insertion testbed to simulate the effects of an SEU on the design under test. The testbed is a board that includes two FPGAs and additional circuitry for comparing output data from the two FPGAs. Each FPGA is configured with the design under test. The configuration data of one of the FPGAs is then deliberately corrupted to simulate the effects of an SEU, by performing a partial reconfiguration and altering (for example) a single configuration bit of the operating design under test. The output data from the two FPGAs is then compared to determine the effects of the simulated SEU.
A disadvantage of this method is that simulating an SEU for each configuration memory cell in an FPGA is not an inconsequential task. For example, in an FPGA having five million configuration bits, testing the results of toggling each bit, one at a time, can be a lengthy process. Considering that this process might need to be performed for many different designs, as the design is modified in an attempt to reduce its susceptibility to SEUs, the process can be undesirably cumbersome. If fewer than all of the five million configuration bits are tested, the results of the test might be skewed. For example, the set of bits tested might include a higher or lower proportion of configuration bits that have no effect on the design functionality than the entire design taken as a whole.
Another disadvantage of this method is that the hardware necessary to perform the simulation testing can be expensive.
An alternative method currently in use is to subject the FPGA, programmed with the design under test, to high energy radiation that can cause SEUS. The high energy radiation can be produced, for example, by high energy particle generators in a lab environment. Conducting these experiments can be time-consuming and costly, as there are only a few facilities available that are capable of performing the experiments.
Therefore, it is desirable to provide simpler and faster methods of estimating the susceptibility to SEUs of a design implemented in an FPGA.